Saturday, February 26, 2011

Ted Smith FGPA DSD dac

The board is dual mono, balanced differential so there is essentially no chance for even order harmonic distortion and I selected my bypassing, etc. to keep the THD below the 120dB noise floor.
To assist in noise control I made sure everything was electrically isolated: output transformers, power supply transformers, AES/EBU and SPDIF transformers, optical connectors for TOSLink or Meitner ST glass DSD.

To save on popcorn logic and to allow easy processing of PCM to DSD I put on a Xilinx FPGA along with the MIPS MCU controlling processor. The FPGA also allows me to avoid other LSI chips like AES/EBU and S/PDIF receivers... No PLLs here.

The board can process:
1) DSD hard wired (well thru a digital isolator)
2) DSD via Meitner orange ST glass
3) TOSLink

The PCM can be 44.1, 48, 88.2, 96, 176.4 or 192.

I synchronously upsample all PCM to 28,224,000 Hz then to double rate DSD (5,644,800 Hz) and also I upsample DSD to double rate DSD.

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